[llvm] [GISEL][RISCV] IRTranslator for scalable vector load (PR #80006)

[Jiahan Xie via llvm-commits]

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@@ -1240,7 +1240,7 @@ void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
        << "unknown-address";
   }
   MachineOperand::printOperandOffset(OS, getOffset());
-  if (getSize() > 0 && getAlign() != getSize())
+  if (getMemoryType().getSizeInBytes().getKnownMinValue() > 0 && getAlign() != getMemoryType().getSizeInBytes().getKnownMinValue())
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jiahanxie353 wrote:

I'm not very confident with this approach. I'm a bit worried if it would this breaks scalar cases.

https://github.com/llvm/llvm-project/pull/80006