[llvm] [GISEL][RISCV] IRTranslator for scalable vector load (PR #80006)

[Jiahan Xie via llvm-commits]

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@@ -0,0 +1,7 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck  -check-prefixes=RV32I %s
+
+define void @vload_vint8m1(ptr %pa) {
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jiahanxie353 wrote:

Sure, I'll add more tests with different types and to include rv64 if this simplest test case makes sense.
Right now, I'm wondering, when I use `llvm/utils/update_mir_test_checks.py `, the `vec-ll.s` file auto-generate `align 8` at the end of `%va = load <vscale x 8 x i8>, ptr %pa`, so I appended it. Does it make sense to add `align 8`?

https://github.com/llvm/llvm-project/pull/80006