[llvm] [GISEL][RISCV] IRTranslator for scalable vector load (PR #80006)

[Michael Maitland via llvm-commits]

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@@ -0,0 +1,7 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck  -check-prefixes=RV32I %s
+
+define void @vload_vint8m1(ptr %pa) {
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michaelmaitland wrote:

I think this is missing test checks. Also, I think we need to test a more complete set of scalable vector types. Lastly, I think we need test checks for rv64 as well.

https://github.com/llvm/llvm-project/pull/80006