[llvm] [AMDGPU] Pick available high VGPR for CSR SGPR spilling (PR #78669)

[Matt Arsenault via llvm-commits]

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@@ -312,6 +312,35 @@ bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
   return false;
 }
 
+void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
+    MachineFunction &MF) {
+  for (unsigned I = 0, E = SpillPhysVGPRs.size(); I < E; ++I) {
+    Register Reg = SpillPhysVGPRs[I];
+    const SIRegisterInfo *TRI =
+        MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+    Register NewReg =
+        TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
+    if (!NewReg || NewReg >= Reg)
+      continue;
+
+    MRI.replaceRegWith(Reg, NewReg);
+
+    // Update various tables with the new VGPR.
+    SpillPhysVGPRs[I] = NewReg;
+    WWMReservedRegs.remove(Reg);
+    WWMReservedRegs.insert(NewReg);
+    WWMSpills.insert(std::make_pair(NewReg, WWMSpills[Reg]));
+    WWMSpills.erase(Reg);
+
+    for (MachineBasicBlock &MBB : MF) {
+      MBB.removeLiveIn(Reg);
+      MBB.addLiveIn(NewReg);
+      MBB.sortUniqueLiveIns();
+    }
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arsenm wrote:

Are these registers still reserved? If so there's no need to do this 

https://github.com/llvm/llvm-project/pull/78669