[llvm] [AMDGPU] Pick available high VGPR for CSR SGPR spilling (PR #78669)

[Matt Arsenault via llvm-commits]

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@@ -369,7 +369,8 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
           // regalloc aware CFI generation to insert new CFIs along with the
           // intermediate spills is implemented. There is no such support
           // currently exist in the LLVM compiler.
-          if (FuncInfo->allocateSGPRSpillToVGPRLane(MF, FI, true)) {
+          if (FuncInfo->allocateSGPRSpillToVGPRLane(
+                  MF, FI, /* SpillToPhysVGPRLane */ true)) {
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arsenm wrote:

Ditto 

https://github.com/llvm/llvm-project/pull/78669