[llvm] [AMDGPU] Pick available high VGPR for CSR SGPR spilling (PR #78669)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 22 00:49:12 PST 2024
================
@@ -312,6 +312,35 @@ bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
return false;
}
+void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
----------------
arsenm wrote:
Maybe this should be commoned with the code to compact the scratch registers
https://github.com/llvm/llvm-project/pull/78669
More information about the llvm-commits
mailing list