[llvm] [AMDGPU] Pick available high VGPR for CSR SGPR spilling (PR #78669)

[Matt Arsenault via llvm-commits]

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@@ -312,6 +312,35 @@ bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
   return false;
 }
 
+void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
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arsenm wrote:

Maybe this should be commoned with the code to compact the scratch registers 

https://github.com/llvm/llvm-project/pull/78669