[llvm] [RISCV] Optimise spills/fills of FPR<->GPR moves (PR #78408)

[Craig Topper via llvm-commits]

================
@@ -97,8 +96,7 @@ define float @spill_i32_to_float(i32 %a) nounwind {
 ; RV64ID-NEXT:    fsd fs9, 24(sp) # 8-byte Folded Spill
 ; RV64ID-NEXT:    fsd fs10, 16(sp) # 8-byte Folded Spill
 ; RV64ID-NEXT:    fsd fs11, 8(sp) # 8-byte Folded Spill
-; RV64ID-NEXT:    fmv.w.x fa5, a0
-; RV64ID-NEXT:    fsw fa5, 4(sp) # 4-byte Folded Spill
+; RV64ID-NEXT:    sd a0, 4(sp) # 4-byte Folded Spill
----------------
topperc wrote:

This says 4-byte spill but its a `sd` instruction and it's probably misaligned.

https://github.com/llvm/llvm-project/pull/78408