[llvm] [RISCV] Optimise spills/fills of FPR<->GPR moves (PR #78408)

[Philip Reames via llvm-commits]

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@@ -763,18 +763,49 @@ MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
     VirtRegMap *VRM) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
 
+  if (Ops.size() != 1)
+    return nullptr;
+  unsigned Opcode = MI.getOpcode();
+
+  // If spilling the destination of a FPR<->GPR move, just store the source
+  // register instead. If filling the source of a FPR<->GPR move, just load
+  // the destination register instead.
+  if (Opcode == RISCV::FMV_D_X || Opcode == RISCV::FMV_W_X ||
+      Opcode == RISCV::FMV_X_D || Opcode == RISCV::FMV_X_W) {
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preames wrote:

For the W variants, aren't the loads and stores different sizes?  In particular the F to lower-32 int case, don't we have to worry about sign extension on rv64?

As a related point, AArch64 has an assertion that the source and destination sizes are the same, and a check that no-subregs are in play.

https://github.com/llvm/llvm-project/pull/78408