[llvm] [RISCV] Support isel for Zacas for 2*XLen types. (PR #77814)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 09:39:17 PST 2024
topperc wrote:
> > RISC-V doesn't always have vector instructions, and the vector iSA does not require a 128-bit vector load to be atomic. It would depend on the microarchitecture.
>
> Yes, that's why I suggested an ISA extension that a given CPU could advertise support for, which _does_ provide that guarantee.
And the lowerings in this patch would require that extension be present?
https://github.com/llvm/llvm-project/pull/77814
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