[llvm] [RISCV] Support isel for Zacas for 2*XLen types. (PR #77814)

[James Y Knight via llvm-commits]

jyknight wrote:

> RISC-V doesn't always have vector instructions, and the vector iSA does not require a 128-bit vector load to be atomic. It would depend on the microarchitecture.

Yes, that's why I suggested an ISA extension that a given CPU could advertise support for, which _does_ provide that guarantee.

https://github.com/llvm/llvm-project/pull/77814