[llvm] [RISCV] Support isel for Zacas for 2*XLen types. (PR #77814)

[James Y Knight via llvm-commits]

jyknight wrote:

> And the lowerings in this patch would require that extension be present?

Yeah.

For RV64 128-bit atomics support: require Zacas, V, and that new extension which promises that 128-bit vector load/store are a single memory operation. Then emit vector instructions for 128-bit atomic load/store.

For RV32 64-bit atomics support: require Zacas, D, and a new extension which promises that 64-bit FLD/FSD are a single memory operation. Emit those for 64-bit atomic load/store.

Alternatively to requiring the V or D extensiosn, an extension implementing integer load/store instructions of double-register widths (reusing the encodings of LQ/SQ in RV64 and LD/SD in RV32, which aren't currently supported) could be nice. I see the latter is actually already proposed in https://github.com/riscv/riscv-zilsd/blob/main/zilsd.adoc. But even with that, you'd still need the previously-described extension promising a single memory operation for double-word load/stores.

https://github.com/llvm/llvm-project/pull/77814