[llvm] [RISCV] Support isel for Zacas for 2*XLen types. (PR #77814)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 08:59:01 PST 2024
topperc wrote:
> > There is no 128-bit atomic load for RISC-V currently defined
>
> Perhaps the simplest path forward to address that would be to define an extension which has no instructions, but simply specifies that a 128-bit vector load or store is a single memory operation. E.g.
>
> ```
> vsetivli zero, 2, e64, m1 # (optionally ta, ma)
> vle64.v v8, (a0)
> vse64.v v8, (a1)
> ```
>
> That'd be analogous to how it's done on x86/aarch64.
RISC-V doesn't always have vector instructions, and the vector iSA does not require a 128-bit vector load to be atomic. It would depend on the microarchitecture.
https://github.com/llvm/llvm-project/pull/77814
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