[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

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Tue Jan 2 21:15:26 PST 2024

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sun-jacobi wrote:

> @sun-jacobi I'm going to revert the patch and let you work on a fix.

Okay, I will fix it soon.

https://github.com/llvm/llvm-project/pull/72340

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