[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

[Craig Topper via llvm-commits]

topperc wrote:

This test case

```
define <vscale x 1 x i32> @foo(<vscale x 1 x i1> %x, <vscale x 1 x i2> %y) {     
  %a = zext <vscale x 1 x i1> %x to <vscale x 1 x i32>                           
  %b = zext <vscale x 1 x i1> %y to <vscale x 1 x i32>                           
  %c = add <vscale x 1 x i32> %a, %b                                             
  ret <vscale x 1 x i32> %c                                                      
}
```

and this test case both fail

```
define <vscale x 1 x i32> @foo(<vscale x 1 x i2> %x, <vscale x 1 x i2> %y) {     
  %a = zext <vscale x 1 x i2> %x to <vscale x 1 x i32>                           
  %b = zext <vscale x 1 x i2> %y to <vscale x 1 x i32>                           
  %c = add <vscale x 1 x i32> %a, %b                                             
  ret <vscale x 1 x i32> %c                                                      
}
```

https://github.com/llvm/llvm-project/pull/72340