[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

[Craig Topper via llvm-commits]

topperc wrote:

We're seeing a failure from this in our testing. We're creating a VZEXT_VL from an i1 vector which isn't supported. I'll see if I can find a quick fix.

https://github.com/llvm/llvm-project/pull/72340