[llvm] [AArch64][SVE] Add optimisation for SVE intrinsics with no active lanes (PR #73964)

[Paul Walker via llvm-commits]

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@@ -1406,9 +1406,23 @@ static std::optional<Instruction *> instCombineSVEAllActive(IntrinsicInst &II,
   return &II;
 }
 
+// Simplify operations where predicate has all inactive lanes or try to replace
+// with _u form when all lanes are active
+static std::optional<Instruction *>
+instCombineSVEAllOrNoActive(InstCombiner &IC, IntrinsicInst &II,
+                            Intrinsic::ID IID) {
+  if (match(II.getOperand(0), m_ZeroInt())) {
+    //  llvm_ir, pred(0), op1, op2 - Spec says to return op1 when all lanes are
+    //  inactive for sv[func]_m or sv[func]_z
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paulwalker-arm wrote:

The `sv[func]_z` part should be removed because those cases should return zero for inactive lanes.

https://github.com/llvm/llvm-project/pull/73964