[llvm] [AArch64][SVE] Add optimisation for SVE intrinsics with no active lanes (PR #73964)

[Paul Walker via llvm-commits]

https://github.com/paulwalker-arm commented:

A couple of minor things but otherwise looks good.  Do you plan to implement a similar optimisation for the unary instructions?

https://github.com/llvm/llvm-project/pull/73964