[llvm] [AArch64][SVE] Add optimisation for SVE intrinsics with no active lanes (PR #73964)

[Paul Walker via llvm-commits]

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@@ -0,0 +1,1448 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; Replace SVE _u intrinsics with undef if the predicate is all false.
+
+; Float arithmetic
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fabd.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+define <vscale x 8 x half> @replace_fabd_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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paulwalker-arm wrote:

This file exists from a previous version of the patch which is no longer applicable to the patch?  So can be removed?

https://github.com/llvm/llvm-project/pull/73964