[llvm] [AArch64] Teach areMemAccessesTriviallyDisjoint about scalable widths. (PR #73655)

[David Sherwood via llvm-commits]

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@@ -1214,8 +1214,7 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
       SEH->eraseFromParent();
   }
 
-  TypeSize Scale = TypeSize::getFixed(1);
-  unsigned Width;
+  TypeSize Scale = TypeSize::getFixed(1), Width(0, false);
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david-arm wrote:

I think it would be nice to use consistent notation here and have 

 TypeSize Scale = TypeSize::getFixed(1), Width = TypeSize::getFixed(0);

https://github.com/llvm/llvm-project/pull/73655