[llvm] [AArch64] Teach areMemAccessesTriviallyDisjoint about scalable widths. (PR #73655)

[David Sherwood via llvm-commits]

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david-arm wrote:

Do we have tests for loads and stores of predicate vectors, i.e. <vscale x 16 x i1>, <vscale x 8 x i1>, <vscale x 4 x i1>, <vscale x 2 x i1>? I'd expect aliasing information to be useful for those cases too.

https://github.com/llvm/llvm-project/pull/73655