[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)

[Craig Topper via llvm-commits]

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@@ -181,3 +181,330 @@ body:             |
     PseudoRET implicit $x10, implicit $x11, implicit $x12
 
 ...
+---
+name:  test_nxv1s8
+body:   |
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topperc wrote:

> I saw you reorganized the testing directory.
> 
> > I think I would prefer a separate test file in test/CodeGen/RISCV/GlobalISel/legalizer/rvv/
> 
> you mean I should create a new folder `rvv/` on top your recent commits? I don't have a strong opinion regarding where to place vector tests, [AArch64 mixed scalar and vector together](https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir) by the way.

Yes. We have separate tests for rv32 and rv64 because the scalar arguments and returns values have different types(s32 vs s64) so the tests aren't the same. AArch64 doesn't have this issue. Vector tests for RISC-V could be identical for rv32 and rv64 as long as they don't contain scalar arguments/returns. So I think its better to have a single test file that has 2 RUN lines so that we don't duplicate identical content in 2 different files.

https://github.com/llvm/llvm-project/pull/71400