[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)
Jiahan Xie via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 18 18:54:48 PST 2023
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@@ -181,3 +181,330 @@ body: |
PseudoRET implicit $x10, implicit $x11, implicit $x12
...
+---
+name: test_nxv1s8
+body: |
----------------
jiahanxie353 wrote:
I saw you reorganized the testing directory.
> I think I would prefer a separate test file in test/CodeGen/RISCV/GlobalISel/legalizer/rvv/
you mean I should create a new folder `rvv/` on top your recent commits?
I don't have a strong opinion regarding where to place vector tests, [AArch64 mixed scalar and vector together](https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir) by the way.
https://github.com/llvm/llvm-project/pull/71400
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