[llvm] TableGen support for RegisterBankInfo (PR #71357)

[via llvm-commits]

================
@@ -289,6 +295,81 @@ void RegisterBankEmitter::emitBaseClassImplementation(
      << "} // end namespace llvm\n";
 }
 
+// RegisterBankInfo tables and enums
+// are discussed in https://discourse.llvm.org/t/74459
+void RegisterBankEmitter::emitRBIHeader(
+    raw_ostream &OS, const StringRef TargetName,
+    const std::vector<RegisterBank> &Banks) {
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+  OS << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n"
+     << "enum PartialMappingIdx {\n"
+     << "  PMI_None = -1,\n";
+
+  // Banks and Register Classes are *not* emitted in their original text order
+  int ID = 0;
+  for (const auto &Bank : Banks) {
+    for (const CodeGenRegisterClass *RC :
+         Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+      OS << "  PMI_" << RC->getName() << " = " << ID++ << ",\n";
+    }
+  }
+  OS << "};\n";
+  OS << "} // end namespace " << TargetName << "\n"
+     << "} // end namespace llvm\n";
+}
+
+void RegisterBankEmitter::emitRBIImplementation(
+    raw_ostream &OS, const StringRef TargetName,
+    const std::vector<RegisterBank> &Banks) {
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+  OS << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n"
+     << "const RegisterBankInfo::PartialMapping PartMappings[] = {\n";
+  for (const auto &Bank : Banks) {
+    for (const CodeGenRegisterClass *RC :
+         Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+      if (RC->RSI.isSimple()) {
+        if (RC->getValueTypes()[0].getSimple() != MVT::Untyped) {
+          // StartIdx is currently 0 in all of the in-tree backends
+          OS << "  { 0, " << RC->RSI.getSimple().RegSize << ", "
+             << Bank.getInstanceVarName() << " },\n";
+        } else {
+          OS << "  #error Untyped RegisterClass " << RC->getName() << "\n";
+        }
+      } else {
+        OS << "  #error non-Simple() RegisterClass " << RC->getName() << "\n";
+      }
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CBSears wrote:

Thanks. I went a little further and reversed both to avoid the continue. It reads a little more clearly and avoids the nesting.

https://github.com/llvm/llvm-project/pull/71357