[llvm] TableGen support for RegisterBankInfo (PR #71357)

[via llvm-commits]

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@@ -13,3 +13,12 @@ let Size = 32 in {
 // CHECK: MyTarget::ClassARegClassID
 // CHECK: MyTarget::ClassBRegClassID
 def GPRRegBank : RegisterBank<"GPR", [ClassA]>;
+
+// CHECK: enum PartialMappingIdx
+// CHECK: PMI_ClassA = 0,
+// CHECK: const RegisterBankInfo::PartialMapping PartMappings
+// CHECK: { 0, 32, GPRRegBank },
+// CHECK: const PartialMappingIdx BankIDToFirstRegisterClassIdx
+// CHECK: PMI_ClassA,
+// CHECK: const int BankIDToRegisterClassCount
+// CHECK: 1,
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CBSears wrote:

Sure. I didn't know about this.

https://github.com/llvm/llvm-project/pull/71357