[llvm] TableGen support for RegisterBankInfo (PR #71357)

[Pierre van Houtryve via llvm-commits]

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@@ -112,7 +112,11 @@ class RegisterBankEmitter {
   void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
                                const std::vector<RegisterBank> &Banks);
   void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
-                                   std::vector<RegisterBank> &Banks);
+                                   const std::vector<RegisterBank> &Banks);
+  void emitRBIHeader(raw_ostream &OS, const StringRef TargetName,
+                     const std::vector<RegisterBank> &Banks);
+  void emitRBIImplementation(raw_ostream &OS, const StringRef TargetName,
+                             const std::vector<RegisterBank> &Banks);
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Pierre-vh wrote:

Up to you. Improving the existing code is always nice but if it's too much of a tangent for this patch I understand as well

https://github.com/llvm/llvm-project/pull/71357