[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Philip Reames via llvm-commits]

https://github.com/preames commented:

As discussed at the dev meeting, I think this is the right overall direction.

In terms of staging, I think it makes sense to first split regalloc in it's own review, and then add the vsetvli variant between them.

I'm concerned by the regressions you mentioned.  Have you investigated them?  In particular, are there any that are cause by splitting RA on it's own?  If they're "only" vsetvli regressions, those are likely less scary and a bit easier to fix.  

https://github.com/llvm/llvm-project/pull/70549