[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Philip Reames via llvm-commits]

================
@@ -494,9 +579,9 @@ class VSETVLIInfo {
     if (hasAVLReg()) {
       if (getAVLReg() == RISCV::X0)
         return true;
-      if (MachineInstr *MI = MRI.getVRegDef(getAVLReg());
-          MI && MI->getOpcode() == RISCV::ADDI &&
-          MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
+      if (MachineInstr *MI = MRI.getUniqueVRegDef(getAVLReg());
+          MI && MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() &&
----------------
preames wrote:

This looks to be stray whitespace change.  Remove.

https://github.com/llvm/llvm-project/pull/70549