[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Philip Reames via llvm-commits]

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@@ -727,20 +812,32 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
   const RISCVSubtarget *ST;
   const TargetInstrInfo *TII;
   MachineRegisterInfo *MRI;
+  LiveIntervals *LIS = nullptr;
 
   std::vector<BlockData> BlockInfo;
   std::queue<const MachineBasicBlock *> WorkList;
+  bool IsSplitRA = false;
 
 public:
   static char ID;
 
-  RISCVInsertVSETVLI() : MachineFunctionPass(ID) {
+  RISCVInsertVSETVLI(bool IsSplitRA = false)
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preames wrote:

In terms of this flag, maybe a better name would be isPostRVVRegAlloc?

https://github.com/llvm/llvm-project/pull/70549