[llvm] 4ac3042 - [RISCV][GISel] Support G_FPEXT/G_FPTRUNC for F and D extension.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 28 16:22:50 PDT 2023
Author: Craig Topper
Date: 2023-10-28T16:22:17-07:00
New Revision: 4ac304242b65413f4eae21af300dd14cb14ed066
URL: https://github.com/llvm/llvm-project/commit/4ac304242b65413f4eae21af300dd14cb14ed066
DIFF: https://github.com/llvm/llvm-project/commit/4ac304242b65413f4eae21af300dd14cb14ed066.diff
LOG: [RISCV][GISel] Support G_FPEXT/G_FPTRUNC for F and D extension.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 7cecc601cea10ca..e80d620936e893b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -197,6 +197,17 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
(ST.hasStdExtD() && typeIs(0, s64)(Query));
});
+ getActionDefinitionsBuilder(G_FPTRUNC).legalIf(
+ [=, &ST](const LegalityQuery &Query) -> bool {
+ return (ST.hasStdExtD() && typeIs(0, s32)(Query) &&
+ typeIs(1, s64)(Query));
+ });
+ getActionDefinitionsBuilder(G_FPEXT).legalIf(
+ [=, &ST](const LegalityQuery &Query) -> bool {
+ return (ST.hasStdExtD() && typeIs(0, s64)(Query) &&
+ typeIs(1, s32)(Query));
+ });
+
getLegacyLegalizerInfo().computeTables();
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 5ad96b812d65ccb..f005948d2094445 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -204,6 +204,30 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
&RISCV::ValueMappings[RISCV::FPR32Idx]});
break;
}
+ case TargetOpcode::G_FPEXT: {
+ LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
+ (void)ToTy;
+ LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
+ (void)FromTy;
+ assert(ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32 &&
+ "Unsupported size for G_FPEXT");
+ OperandsMapping =
+ getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR64Idx],
+ &RISCV::ValueMappings[RISCV::FPR32Idx]});
+ break;
+ }
+ case TargetOpcode::G_FPTRUNC: {
+ LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
+ (void)ToTy;
+ LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
+ (void)FromTy;
+ assert(ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64 &&
+ "Unsupported size for G_FPTRUNC");
+ OperandsMapping =
+ getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR32Idx],
+ &RISCV::ValueMappings[RISCV::FPR64Idx]});
+ break;
+ }
default:
return getInvalidInstructionMapping();
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc.mir
new file mode 100644
index 000000000000000..9f0de60dab78278
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc.mir
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fpext
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fpext
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FCVT_D_S:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_S [[COPY]], 0
+ ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_S]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:fprb(s32) = COPY $f10_f
+ %1:fprb(s64) = G_FPEXT %0(s32)
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fptrunc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptrunc
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FCVT_S_D:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_D [[COPY]], 7
+ ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_D]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:fprb(s64) = COPY $f10_d
+ %1:fprb(s32) = G_FPTRUNC %0(s64)
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc.mir
new file mode 100644
index 000000000000000..29355f50dc4b429
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc.mir
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: fpext
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fpext
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
+ ; CHECK-NEXT: $f10_d = COPY [[FPEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s32) = COPY $f10_f
+ %1:_(s64) = G_FPEXT %0(s32)
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fptrunc
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptrunc
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $f10_f = COPY [[FPTRUNC]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTRUNC %0(s64)
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
new file mode 100644
index 000000000000000..1ed7ceea2f6509a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: fpext
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fpext
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:fprb(s64) = G_FPEXT [[COPY]](s32)
+ ; CHECK-NEXT: $f10_d = COPY [[FPEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s32) = COPY $f10_f
+ %1:_(s64) = G_FPEXT %0(s32)
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fptrunc
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptrunc
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:fprb(s32) = G_FPTRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $f10_f = COPY [[FPTRUNC]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTRUNC %0(s64)
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
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