[llvm] 49ae2ef - [RISCV][GISel] Support G_FMA/NEG/ABS/SQRT/MAXNUM/MINNUM for F and D extension.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 28 15:54:36 PDT 2023
Author: Craig Topper
Date: 2023-10-28T15:53:15-07:00
New Revision: 49ae2efb809db20603d500f02dd278247b542c73
URL: https://github.com/llvm/llvm-project/commit/49ae2efb809db20603d500f02dd278247b542c73
DIFF: https://github.com/llvm/llvm-project/commit/49ae2efb809db20603d500f02dd278247b542c73.diff
LOG: [RISCV][GISel] Support G_FMA/NEG/ABS/SQRT/MAXNUM/MINNUM for F and D extension.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index ac6a887ed5d827c..7cecc601cea10ca 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -190,7 +190,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
// FP Operations
- getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
+ getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FNEG,
+ G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM})
.legalIf([=, &ST](const LegalityQuery &Query) -> bool {
return (ST.hasStdExtF() && typeIs(0, s32)(Query)) ||
(ST.hasStdExtD() && typeIs(0, s64)(Query));
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 2a99a7174f88eab..5ad96b812d65ccb 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -178,13 +178,32 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB:
case TargetOpcode::G_FMUL:
- case TargetOpcode::G_FDIV: {
+ case TargetOpcode::G_FDIV:
+ case TargetOpcode::G_FNEG:
+ case TargetOpcode::G_FABS:
+ case TargetOpcode::G_FSQRT:
+ case TargetOpcode::G_FMAXNUM:
+ case TargetOpcode::G_FMINNUM: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
OperandsMapping = Ty.getSizeInBits() == 64
? &RISCV::ValueMappings[RISCV::FPR64Idx]
: &RISCV::ValueMappings[RISCV::FPR32Idx];
break;
}
+ case TargetOpcode::G_FMA: {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ OperandsMapping =
+ Ty.getSizeInBits() == 64
+ ? getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR64Idx],
+ &RISCV::ValueMappings[RISCV::FPR64Idx],
+ &RISCV::ValueMappings[RISCV::FPR64Idx],
+ &RISCV::ValueMappings[RISCV::FPR64Idx]})
+ : getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR32Idx],
+ &RISCV::ValueMappings[RISCV::FPR32Idx],
+ &RISCV::ValueMappings[RISCV::FPR32Idx],
+ &RISCV::ValueMappings[RISCV::FPR32Idx]});
+ break;
+ }
default:
return getInvalidInstructionMapping();
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
index 0a4fa10ba0b67e5..865ade4f3170cfd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
@@ -99,6 +99,98 @@ body: |
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f
+...
+---
+name: fma_f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f, $f12_f
+
+ ; CHECK-LABEL: name: fma_f32
+ ; CHECK: liveins: $f10_f, $f11_f, $f12_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f12_f
+ ; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nofpexcept FMADD_S [[COPY]], [[COPY1]], [[COPY2]], 7
+ ; CHECK-NEXT: $f10_f = COPY [[FMADD_S]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:fprb(s32) = COPY $f10_f
+ %1:fprb(s32) = COPY $f11_f
+ %2:fprb(s32) = COPY $f12_f
+ %3:fprb(s32) = G_FMA %0, %1, %2
+ $f10_f = COPY %3(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fneg_f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f, $f12_f
+
+ ; CHECK-LABEL: name: fneg_f32
+ ; CHECK: liveins: $f10_f, $f11_f, $f12_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FSGNJN_S:%[0-9]+]]:fpr32 = FSGNJN_S [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FSGNJN_S]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:fprb(s32) = COPY $f10_f
+ %1:fprb(s32) = G_FNEG %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fabs_f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f, $f12_f
+
+ ; CHECK-LABEL: name: fabs_f32
+ ; CHECK: liveins: $f10_f, $f11_f, $f12_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FSGNJX_S:%[0-9]+]]:fpr32 = FSGNJX_S [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FSGNJX_S]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:fprb(s32) = COPY $f10_f
+ %1:fprb(s32) = G_FABS %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fsqrt_f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f, $f12_f
+
+ ; CHECK-LABEL: name: fsqrt_f32
+ ; CHECK: liveins: $f10_f, $f11_f, $f12_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FSQRT_S:%[0-9]+]]:fpr32 = nofpexcept FSQRT_S [[COPY]], 7
+ ; CHECK-NEXT: $f10_f = COPY [[FSQRT_S]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:fprb(s32) = COPY $f10_f
+ %1:fprb(s32) = G_FSQRT %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
...
---
name: fadd_f64
@@ -123,6 +215,54 @@ body: |
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d
+...
+---
+name: fmaxnum_f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fmaxnum_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
+ ; CHECK-NEXT: [[FMAX_S:%[0-9]+]]:fpr32 = nofpexcept FMAX_S [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_f = COPY [[FMAX_S]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:fprb(s32) = COPY $f10_f
+ %1:fprb(s32) = COPY $f11_f
+ %2:fprb(s32) = G_FMAXNUM %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fminnum_f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fminnum_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
+ ; CHECK-NEXT: [[FMIN_S:%[0-9]+]]:fpr32 = nofpexcept FMIN_S [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_f = COPY [[FMIN_S]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:fprb(s32) = COPY $f10_f
+ %1:fprb(s32) = COPY $f11_f
+ %2:fprb(s32) = G_FMINNUM %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
...
---
name: fsub_f64
@@ -196,3 +336,143 @@ body: |
PseudoRET implicit $f10_d
...
+---
+name: fma_f64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d, $f12_d
+
+ ; CHECK-LABEL: name: fma_f64
+ ; CHECK: liveins: $f10_d, $f11_d, $f12_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f12_d
+ ; CHECK-NEXT: [[FMADD_D:%[0-9]+]]:fpr64 = nofpexcept FMADD_D [[COPY]], [[COPY1]], [[COPY2]], 7
+ ; CHECK-NEXT: $f10_d = COPY [[FMADD_D]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:fprb(s64) = COPY $f10_d
+ %1:fprb(s64) = COPY $f11_d
+ %2:fprb(s64) = COPY $f12_d
+ %3:fprb(s64) = G_FMA %0, %1, %2
+ $f10_d = COPY %3(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fneg_f64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fneg_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FSGNJN_D:%[0-9]+]]:fpr64 = FSGNJN_D [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $f10_d = COPY [[FSGNJN_D]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:fprb(s64) = COPY $f10_d
+ %1:fprb(s64) = G_FNEG %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fabs_f64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fabs_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FSGNJX_D:%[0-9]+]]:fpr64 = FSGNJX_D [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $f10_d = COPY [[FSGNJX_D]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:fprb(s64) = COPY $f10_d
+ %1:fprb(s64) = G_FABS %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fsqrt_f64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fsqrt_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FSQRT_D:%[0-9]+]]:fpr64 = nofpexcept FSQRT_D [[COPY]], 7
+ ; CHECK-NEXT: $f10_d = COPY [[FSQRT_D]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:fprb(s64) = COPY $f10_d
+ %1:fprb(s64) = G_FSQRT %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fmaxnum_f64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fmaxnum_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
+ ; CHECK-NEXT: [[FMAX_D:%[0-9]+]]:fpr64 = nofpexcept FMAX_D [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_d = COPY [[FMAX_D]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:fprb(s64) = COPY $f10_d
+ %1:fprb(s64) = COPY $f11_d
+ %2:fprb(s64) = G_FMAXNUM %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fminnum_f64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fminnum_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
+ ; CHECK-NEXT: [[FMIN_D:%[0-9]+]]:fpr64 = nofpexcept FMIN_D [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_d = COPY [[FMIN_D]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:fprb(s64) = COPY $f10_d
+ %1:fprb(s64) = COPY $f11_d
+ %2:fprb(s64) = G_FMINNUM %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
index e6a6c695e145b5f..e7bb8dfd89daeeb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
@@ -87,6 +87,128 @@ body: |
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f
+...
+---
+name: fma_f32
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f, $f12_f
+
+ ; CHECK-LABEL: name: fma_f32
+ ; CHECK: liveins: $f10_f, $f11_f, $f12_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_f = COPY [[FMA]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = COPY $f11_f
+ %2:_(s32) = COPY $f12_f
+ %3:_(s32) = G_FMA %0, %1, %2
+ $f10_f = COPY %3(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fneg_f32
+body: |
+ bb.0:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fneg_f32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FNEG]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FNEG %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fabs_f32
+body: |
+ bb.0:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fabs_f32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FABS]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FABS %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fsqrt_f32
+body: |
+ bb.0:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fsqrt_f32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FSQRT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FSQRT %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fmaxnum_f32
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fmaxnum_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_f = COPY [[FMAXNUM]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = COPY $f11_f
+ %2:_(s32) = G_FMAXNUM %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fminnum_f32
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fminnum_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_f = COPY [[FMINNUM]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = COPY $f11_f
+ %2:_(s32) = G_FMINNUM %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
...
---
name: fadd_f64
@@ -172,3 +294,125 @@ body: |
PseudoRET implicit $f10_d
...
+---
+name: fma_f64
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d, $f12_d
+
+ ; CHECK-LABEL: name: fma_f64
+ ; CHECK: liveins: $f10_d, $f11_d, $f12_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f12_d
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_d = COPY [[FMA]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = COPY $f11_d
+ %2:_(s64) = COPY $f12_d
+ %3:_(s64) = G_FMA %0, %1, %2
+ $f10_d = COPY %3(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fneg_f64
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fneg_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]]
+ ; CHECK-NEXT: $f10_d = COPY [[FNEG]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FNEG %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fabs_f64
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fabs_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
+ ; CHECK-NEXT: $f10_d = COPY [[FABS]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FABS %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fsqrt_f64
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fsqrt_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
+ ; CHECK-NEXT: $f10_d = COPY [[FSQRT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FSQRT %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fmaxnum_f64
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fmaxnum_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s64) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_d = COPY [[FMAXNUM]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = COPY $f11_d
+ %2:_(s64) = G_FMAXNUM %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fminnum_f64
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fminnum_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s64) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_d = COPY [[FMINNUM]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = COPY $f11_d
+ %2:_(s64) = G_FMINNUM %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
index 0fc708b5bb1f3d2..1933678daef7b50 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
@@ -97,6 +97,140 @@ body: |
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f
+...
+---
+name: fma_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f, $f12_f
+
+ ; CHECK-LABEL: name: fma_f32
+ ; CHECK: liveins: $f10_f, $f11_f, $f12_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f12_f
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:fprb(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_f = COPY [[FMA]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = COPY $f11_f
+ %2:_(s32) = COPY $f12_f
+ %3:_(s32) = G_FMA %0, %1, %2
+ $f10_f = COPY %3(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fneg_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fneg_f32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:fprb(s32) = G_FNEG [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FNEG]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FNEG %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fabs_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fabs_f32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FABS]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FABS %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fsqrt_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fsqrt_f32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FSQRT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FSQRT %0
+ $f10_f = COPY %1(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fmaxnum_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fmaxnum_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:fprb(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_f = COPY [[FMAXNUM]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = COPY $f11_f
+ %2:_(s32) = G_FMAXNUM %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fminnum_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fminnum_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:fprb(s32) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_f = COPY [[FMINNUM]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = COPY $f11_f
+ %2:_(s32) = G_FMINNUM %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
...
---
name: fadd_f64
@@ -190,3 +324,137 @@ body: |
PseudoRET implicit $f10_d
...
+---
+name: fma_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d, $f12_d
+
+ ; CHECK-LABEL: name: fma_f64
+ ; CHECK: liveins: $f10_d, $f11_d, $f12_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f12_d
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:fprb(s64) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_d = COPY [[FMA]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = COPY $f11_d
+ %2:_(s64) = COPY $f12_d
+ %3:_(s64) = G_FMA %0, %1, %2
+ $f10_d = COPY %3(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fneg_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fneg_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:fprb(s64) = G_FNEG [[COPY]]
+ ; CHECK-NEXT: $f10_d = COPY [[FNEG]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FNEG %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fabs_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fabs_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
+ ; CHECK-NEXT: $f10_d = COPY [[FABS]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FABS %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fsqrt_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fsqrt_f64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]]
+ ; CHECK-NEXT: $f10_d = COPY [[FSQRT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FSQRT %0
+ $f10_d = COPY %1(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fmaxnum_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fmaxnum_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:fprb(s64) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_d = COPY [[FMAXNUM]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = COPY $f11_d
+ %2:_(s64) = G_FMAXNUM %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
+---
+name: fminnum_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fminnum_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:fprb(s64) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_d = COPY [[FMINNUM]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = COPY $f11_d
+ %2:_(s64) = G_FMINNUM %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
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