[llvm] [AMDGPU] Set Size to 4 for V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO (PR #70376)

[Joe Nash via llvm-commits]

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@@ -132,7 +132,7 @@ def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
   let isAsCheapAsAMove = 1;
   let isMoveImm = 1;
   let SchedRW = [Write64Bit];
-  let Size = 16; // Needs maximum 2 v_mov_b32 instructions 8 byte long each.
+  let Size = 4;
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Sisyph wrote:

It seems like getInstSizeInBytes will return the true size, neither min nor max. And I agree TableGen Size an intermediate target defined value. We should Size it consistently on the AMDGPU target. I think it is minimum size. There does not appear to be a natural place to document it, but perhaps as a comment on SIInstrInfo::getInstSizeInBytes. Please consider that a nit, otherwise the patch looks good.

https://github.com/llvm/llvm-project/pull/70376