[llvm] [RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (PR #70266)

[Michael Maitland via llvm-commits]

================
@@ -62,6 +62,45 @@ multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,
     def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
 }
 
+// Define a SchedAlias for the SchedWrite associated with (name, mx) whose
+// behavior is aliased to a Variant. The Variant has Latency predLad and
+// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has
+// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite
+// is created similiarly if IsWorstCase is true. The prefix is used to uniquely
+// define SchedWriteRes and Variant resources.
+multiclass LMULWriteResMXVariant<string name, SchedPredicate Pred,
+                                 list<ProcResourceKind> resources,
+                                 int predLat, list<int> predCycles,
+                                 int noPredLat, list<int> noPredCycles,
+                                 string mx, bit IsWorstCase, string prefix> {
+  defvar nameMX = prefix # name # "_" # mx;
+
+  // Define the different behaviors
+  def nameMX # "_Pred" : SchedWriteRes<resources>
----------------
michaelmaitland wrote:

> What's wrong with the Name being applied to the SchedAlias?

Say we had something like this:
```
defm "SiFive7" : LMULWriteResMXVariant<"WriteVLDS8",  VLDSX0Pred, [SiFive7VL],
```

Then when we define a SchedWriteRes using LMULWriteResMXVariant, then it also gets "SiFIve7" prepended to it, creating something like "SiFive7VLDS_M1_Pred". Then to create the variant, we must have that prefix:

```
   // Tie behavior to predicate
   def nameMX # "_Variant" : SchedWriteVariant<[
-    SchedVar<Pred, [!cast<SchedWriteRes>(nameMX # "_Pred")]>,
-    SchedVar<NoSchedPred, [!cast<SchedWriteRes>(nameMX # "_NoPred")]>
+    SchedVar<Pred, [!cast<SchedWriteRes>("SiFive7" # nameMX # "_Pred")]>,
+    SchedVar<NoSchedPred, [!cast<SchedWriteRes>("SiFive7" # nameMX # "_NoPred")]>
   ]>;
   def : SchedAlias<
-    !cast<SchedReadWrite>(name # "_" # mx),
-    !cast<SchedReadWrite>(nameMX # "_Variant")>;
+    !cast<SchedReadWrite>(nameMX),
+    !cast<SchedReadWrite>("SiFive7" # nameMX # "_Variant")>;
```

The problem here is that we need to know the prefix anyway, to create the Variant and SchedAlias, so specifying it in the `defm` achieves absolutely nothing.

The only alternative I can think of is for us to use something like `LMULSchedWritesVariant` similiar to `LMULSchedWrites` to be used in conjunction with `LMULWriteResVariant`. However, I don't think this is the right approach either because this would force all subtargets to use a variant in those places, even if they didn't need to use a variant. I think the current approach may be the best approach.

https://github.com/llvm/llvm-project/pull/70266