[llvm] [RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (PR #70266)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 26 04:53:01 PDT 2023
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@@ -455,11 +455,20 @@ foreach mx = SchedMxList in {
// specific suffixes, but since SEW is already encoded in the name of the
// resource, we do not need to use LMULSEWXXX constructors. However, we do
// use the SEW from the name to determine the number of Cycles.
+
+// This predicate is true when the rs2 operand of vlse or vsse is x0, false
+// otherwise.
+def VLDSX0Pred: SchedPredicate<[{ MI->getOperand(3).getReg() == RISCV::X0 }]>;
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wangpc-pp wrote:
Can this be rewritten by `CheckRegOperand` defined in `TargetInstrPredicate.td`?
https://github.com/llvm/llvm-project/pull/70266
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