[llvm] [AArch64] Clarify that Anyext is OK for MOPS instructions. NFC (PR #70298)
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Thu Oct 26 01:05:31 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
The instruction should only read the bottom 8 bits of the register, so an anyext is OK here. Update the comment from zext->anyext to clarify.
Closes #<!-- -->70270
---
Full diff: https://github.com/llvm/llvm-project/pull/70298.diff
1 Files Affected:
- (modified) llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (+4-2)
``````````diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 9fadc008de20628..6c1d25f62c21e76 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1253,7 +1253,8 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
}
case Intrinsic::aarch64_mops_memset_tag: {
assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
- // Zext the value to 64 bit
+ // Anyext the value being set to 64 bit (only the bottom 8 bits are read by
+ // the instruction).
MachineIRBuilder MIB(MI);
auto &Value = MI.getOperand(3);
Register ZExtValueReg = MIB.buildAnyExt(LLT::scalar(64), Value).getReg(0);
@@ -1776,7 +1777,8 @@ bool AArch64LegalizerInfo::legalizeMemOps(MachineInstr &MI,
// Tagged version MOPSMemorySetTagged is legalised in legalizeIntrinsic
if (MI.getOpcode() == TargetOpcode::G_MEMSET) {
- // Zext the value operand to 64 bit
+ // Anyext the value being set to 64 bit (only the bottom 8 bits are read by
+ // the instruction).
auto &Value = MI.getOperand(1);
Register ZExtValueReg =
MIRBuilder.buildAnyExt(LLT::scalar(64), Value).getReg(0);
``````````
</details>
https://github.com/llvm/llvm-project/pull/70298
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