[llvm] [AArch64][GlobalISel] Add support for pre-indexed loads/stores. (PR #70185)

[Amara Emerson via llvm-commits]

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@@ -5659,24 +5659,34 @@ bool AArch64InstructionSelector::selectIndexedLoad(MachineInstr &MI,
   Register WriteBack = Ld.getWritebackReg();
   Register Base = Ld.getBaseReg();
   Register Offset = Ld.getOffsetReg();
-
-  if (Ld.isPre())
-    return false; // TODO: add pre-inc support
-
-  unsigned Opc = 0;
-  static constexpr unsigned GPROpcodes[] = {
-      AArch64::LDRBBpost, AArch64::LDRHHpost, AArch64::LDRWpost,
-      AArch64::LDRXpost};
-  static constexpr unsigned FPROpcodes[] = {
-      AArch64::LDRBpost, AArch64::LDRHpost, AArch64::LDRSpost,
-      AArch64::LDRDpost, AArch64::LDRQpost};
-
+  LLT Ty = MRI.getType(Dst);
+  assert(Ty.getSizeInBits() <= 128 && "Unexpected type for indexed load");
   unsigned MemSize = Ld.getMMO().getMemoryType().getSizeInBytes();
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aemerson wrote:

Good question. We have separate opcodes for extending loads, `G_INDEXED_ZEXTLOAD/G_INDEXED_SEXTLOAD`. If the load's destination type is > memory type here it's an any extending load, so we just use the memory type to decide which instruction to pick.

https://github.com/llvm/llvm-project/pull/70185