[llvm] [AArch64][GlobalISel] Add support for pre-indexed loads/stores. (PR #70185)
Jon Roelofs via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 25 09:49:53 PDT 2023
================
@@ -5659,24 +5659,34 @@ bool AArch64InstructionSelector::selectIndexedLoad(MachineInstr &MI,
Register WriteBack = Ld.getWritebackReg();
Register Base = Ld.getBaseReg();
Register Offset = Ld.getOffsetReg();
-
- if (Ld.isPre())
- return false; // TODO: add pre-inc support
-
- unsigned Opc = 0;
- static constexpr unsigned GPROpcodes[] = {
- AArch64::LDRBBpost, AArch64::LDRHHpost, AArch64::LDRWpost,
- AArch64::LDRXpost};
- static constexpr unsigned FPROpcodes[] = {
- AArch64::LDRBpost, AArch64::LDRHpost, AArch64::LDRSpost,
- AArch64::LDRDpost, AArch64::LDRQpost};
-
+ LLT Ty = MRI.getType(Dst);
+ assert(Ty.getSizeInBits() <= 128 && "Unexpected type for indexed load");
unsigned MemSize = Ld.getMMO().getMemoryType().getSizeInBytes();
----------------
jroelofs wrote:
dumb question: are we guaranteed that `Ty.getSizeInBits() == MemSize`, or could the size of the memory operand be wider than what's actually loaded?
https://github.com/llvm/llvm-project/pull/70185
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