[llvm] [RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (PR #69788)

[Philip Reames via llvm-commits]

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@@ -1101,21 +1101,20 @@ define void @urem_v2i64(ptr %x, ptr %y) {
 define void @mulhu_v16i8(ptr %x) {
 ; CHECK-LABEL: mulhu_v16i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
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preames wrote:

Actually, I'm wrong here.  Ignore this.

The alignment is not tied to LMUL for these instructions, it's tied to EMUL.  The EMUL of the load hasn't changed here, and thus this is still fine.  

https://github.com/llvm/llvm-project/pull/69788