[llvm] [RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (PR #69788)

[Philip Reames via llvm-commits]

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@@ -1101,21 +1101,20 @@ define void @urem_v2i64(ptr %x, ptr %y) {
 define void @mulhu_v16i8(ptr %x) {
 ; CHECK-LABEL: mulhu_v16i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
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preames wrote:

I don't think this change is correct.  (Well, the reasoning that got here.)

The problem is that increasing LMUL beyond m1 increases the register alignment requirement for the register group.  In this case, v8 happens to be a valid LMUL2 register group, but I don't think there's anything that guarantees that by construction.  

I think the reasoning in your change is fine here - it's causing the forward flow over the vmv.s.x.  It's the existing backward pass which appears to be exposing the bug here.  I think our problem is basically that we need three states for LMUL - ignored, demanded, and alignment demanded. 

https://github.com/llvm/llvm-project/pull/69788