[llvm] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

[Craig Topper via llvm-commits]

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@@ -936,7 +936,9 @@ def : ReadAdvance<ReadFMA16, 0>;
 def : ReadAdvance<ReadFMul32, 0>;
 def : ReadAdvance<ReadFMul64, 0>;
 def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA32Addend, 0>;
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topperc wrote:

Please make FMA16 consistent

https://github.com/llvm/llvm-project/pull/70232