[llvm] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

[Michael Maitland via llvm-commits]

================
@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
 } // Predicates = [HasStdExtF]
 
 foreach Ext = FExts in {
-  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
----------------
michaelmaitland wrote:

Should this change be in a separate commit?

https://github.com/llvm/llvm-project/pull/70232