[llvm] [AMDGPU] Add writelane and readlane pseudos for SGPR spilling (PR #69923)

[Carl Ritson via llvm-commits]

================
@@ -4301,7 +4311,9 @@ static bool shouldReadExec(const MachineInstr &MI) {
   if (SIInstrInfo::isVALU(MI)) {
     switch (MI.getOpcode()) {
     case AMDGPU::V_READLANE_B32:
+    case AMDGPU::SI_RELOAD_S32_FROM_VGPR:
----------------
perlfu wrote:

Not sure we want this?

https://github.com/llvm/llvm-project/pull/69923