[llvm] Add RV64 constraint to SRLIW (PR #69416)

[Craig Topper via llvm-commits]

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@@ -2680,7 +2681,7 @@ bool RISCVDAGToDAGISel::selectSHXADDOp(SDValue N, unsigned ShAmt,
     if (N0.getOpcode() == ISD::AND && N0.hasOneUse() &&
         isa<ConstantSDNode>(N0.getOperand(1))) {
       uint64_t Mask = N0.getConstantOperandVal(1);
-      if (isShiftedMask_64(Mask)) {
+      if (isShiftedMask_64(Mask) && Subtarget->is64Bit()) {
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topperc wrote:

This shoudl be protected by Leading == 32.

https://github.com/llvm/llvm-project/pull/69416