[llvm] Add RV64 constraint to SRLIW (PR #69416)

[Craig Topper via llvm-commits]

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@@ -1143,7 +1143,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
         unsigned Leading = XLen - llvm::bit_width(C1);
         if (C2 < Leading) {
           // If the number of leading zeros is C2+32 this can be SRLIW.
-          if (C2 + 32 == Leading) {
+          if (C2 + 32 == Leading && Subtarget->is64Bit()) {
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topperc wrote:

This should already be protected by the use of XLen in the calculation of `Leading`.

https://github.com/llvm/llvm-project/pull/69416