[llvm] Add RV64 constraint to SRLIW (PR #69416)

[Craig Topper via llvm-commits]

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@@ -1157,7 +1157,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
           // legalized and goes through DAG combine.
           if (C2 >= 32 && (Leading - C2) == 1 && N0.hasOneUse() &&
               X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
-              cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32) {
+              cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32 &&
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topperc wrote:

This is also protected already by the C2 >= 32 check and a sext_inreg with MVT::i32 would also be illegal on RV32.

https://github.com/llvm/llvm-project/pull/69416