[llvm] Add RV64 constraint to SRLIW (PR #69416)

[Craig Topper via llvm-commits]

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@@ -984,7 +984,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
 
     // Optimize (srl (and X, C2), C) -> (slli (srliw X, C3), C3-C) where C2 has
     // 32 leading zeros and C3 trailing zeros.
-    if (isShiftedMask_64(Mask) && N0.hasOneUse()) {
+    if (isShiftedMask_64(Mask) && N0.hasOneUse() && Subtarget->is64Bit()) {
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topperc wrote:

So is this one.

https://github.com/llvm/llvm-project/pull/69416