[llvm] Add RV64 constraint to SRLIW (PR #69416)

[Craig Topper via llvm-commits]

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@@ -1014,7 +1014,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     if (ShAmt >= TrailingOnes)
       break;
     // If the mask has 32 trailing ones, use SRLIW.
-    if (TrailingOnes == 32) {
+    if (TrailingOnes == 32 && Subtarget->is64Bit()) {
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topperc wrote:

I agree this one is buggy.

https://github.com/llvm/llvm-project/pull/69416