[llvm] [RISCV] Combine trunc (srl zext (x), zext (y)) to srl (x, umin (y, scalarsizeinbits(y) - 1)) (PR #69092)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 16 10:24:15 PDT 2023

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topperc wrote:

Is https://github.com/llvm/llvm-project/pull/65728 also broken?

https://github.com/llvm/llvm-project/pull/69092

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