[llvm] [RISCV] Combine trunc (srl zext (x), zext (y)) to srl (x, umin (y, scalarsizeinbits(y) - 1)) (PR #69092)

[via llvm-commits]

LWenH wrote:

https://github.com/llvm/llvm-project/pull/65728 is still work. This is actually quite a tricky but interesting question about the rvv spec I think, such optimization can't work for srl, but it's work for sra. The vsrl I think  in the rvv spec should not only define the lg2(sew) as shift amount, like above examle, the shift amount is valid where y is 8, but for vsra, 7 is the maximum shift amount.

I think RVV Spec should seperate this lg2(sew) restriction for vsrl and vsra.

https://github.com/llvm/llvm-project/pull/69092