[llvm] [RISCV] Combine trunc (srl zext (x), zext (y)) to srl (x, umin (y, scalarsizeinbits(y) - 1)) (PR #69092)

[Luke Lau via llvm-commits]

lukel97 wrote:

Yeah, but it looks like GCC is still able to perform the vsrl on the narrower SEW with vminu.vv from this C example: https://gcc.godbolt.org/z/r5refhWc9 
Is there another combine we're able to add for this? 

https://github.com/llvm/llvm-project/pull/69092