[llvm] [AArch64] Fix for misched-branch-targets.mir test (PR #68424)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

<details>
<summary>Changes</summary>

Fix test failure in non-assertion builds introduced by f1b2dd2a111f038420b3f69d4ce0b3b3f245c873.

---
Full diff: https://github.com/llvm/llvm-project/pull/68424.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/AArch64/misched-branch-targets.mir (+3) 


``````````diff
diff --git a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
index f32c1e964f97356..ce11b095f6176ab 100644
--- a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
+++ b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
@@ -1,6 +1,9 @@
 # RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
 # RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
 
+; REQUIRES: asserts
+; -misched=shuffle is only available with assertions enabled
+
 # Check that instructions that are recognized as branch targets by BTI
 # are not reordered by machine instruction schedulers.
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/68424